Wednesday 8 July 2015

Operating Systems

A CPU generates 32-bit virtual addresses. The page size is 4 KB. The processor has a translation look-aside buffer (TLB) which can hold a total of 128 page table entries and is 4-way set associative. The minimum size of the TLB tag is:
(A) 11 bits
(B) 13 bits
(C) 15 bits
(D) 20 bits

Answer: (C) 

Explanation: Size of a page = 4KB = 2^12
Total number of bits needed to address a page frame = 32 – 12 = 20
If there are ‘n’ cache lines in a set, the cache placement is called n-way set associative. Since TLB is 4 way set associative and can hold total 128 (2^7) page table entries, number of sets in cache = 2^7/4 = 2^5. So 5 bits are needed to address a set, and 15 (20 – 5) bits are needed for tag.

Consider data given in the above question. What is the minimum number of page colours needed to guarantee that no two synonyms map to different sets in the processor cache of this computer? (GATE CS 2013)
(A) 2
(B) 4
(C) 8
(D) 16


Answer: (C)

Explanation:
1 MB 16-way set associative virtually indexed physically tagged cache(VIPT). 
The cache block size is 64 bytes.

No of blocks is 2^20/2^6 = 2^14.

No of sets is 2^14/2^4 = 2^10.

VA(46)
+-------------------------------+
tag(30) , Set(10) , block offset(6)
+-------------------------------+

In VIPT if the no. of bits of page offset = 
                  (Set+block offset) then only one page color is sufficient.

but we need 8 colors because the number bits where the cache set index and 
physical page number over lap is 3 so 2^3 page colors is required.(option 
c is ans). 

Virtual memory is
(A) Large secondary memory
(B) Large main memory
(C) Illusion of large main memory
(D) None of the above

Answer: (C) 

Explanation: Virtual memory is illusion of large main memory.

No comments:

Post a Comment